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C8051F380/1/2/3/4/5/6/7/C
SFR Definition 26.19. TMR4CN: Timer 4 Control
Bit
Name
Type
Reset
7
TF4H
R/W
0
6
TF4L
R/W
0
5
TF4LEN
R/W
0
4
R
0
3
T4SPLIT
R/W
0
2
TR4
R/W
0
1
R
0
0
T4XCLK
R/W
0
SFR Address = 0x91; SFR Page = F
Bit Name
Function
7
6
5
4
3
2
1
0
290
TF4H
TF4L
TF4LEN
Unused
T4SPLIT
TR4
Unused
T4XCLK
Timer 4 High Byte Overflow Flag.
Set by hardware when the Timer 4 high byte overflows from 0xFF to 0x00. In 16 bit
mode, this will occur when Timer 4 overflows from 0xFFFF to 0x0000. When the
Timer 4 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 4
interrupt service routine. This bit is not automatically cleared by hardware.
Timer 4 Low Byte Overflow Flag.
Set by hardware when the Timer 4 low byte overflows from 0xFF to 0x00. TF4L will
be set when the low byte overflows regardless of the Timer 4 mode. This bit is not
automatically cleared by hardware.
Timer 4 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 4 Low Byte interrupts. If Timer 4 interrupts are
also enabled, an interrupt will be generated when the low byte of Timer 4 overflows.
Read = 0b; Write = don’t care.
Timer 4 Split Mode Enable.
When this bit is set, Timer 4 operates as two 8-bit timers with auto-reload.
0: Timer 4 operates in 16-bit auto-reload mode.
1: Timer 4 operates as two 8-bit auto-reload timers.
Timer 4 Run Control.
Timer 4 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
TMR4H only; TMR4L is always enabled in split mode.
Read = 0b; Write = don’t care.
Timer 4 External Clock Select.
This bit selects the external clock source for Timer 4. However, the Timer 4 Clock
Select bits (T4MH and T4ML in register CKCON1) may still be used to select
between the external clock and the system clock for either timer.
0: Timer 4 clock is the system clock divided by 12.
1: Timer 4 clock is the external clock divided by 8 (synchronized with SYSCLK).
Rev. 1.4
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